Google Design Verification Engineer, ASIC, Platforms in Sunnyvale, California
Bachelor's degree or equivalent practical experience.
3 years of experience in the verification of designs such as CPUs, networking, or peripheral controllers.
Experience with verification methodologies (such as UVM, VVM, OVM).
Experience with SystemVerilog, SVA, and functional coverage.
Master's degree in Electrical Engineering.
8 years of industry experience.
Experience with the full verification lifecycle and developing and executing test plans for Block/Sub-System/SOC level verification.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience with PCIe, TCP/IP, UDP, RDMA, NVMe, NVMeOF and understanding of ARM interconnect protocols APB/AXI/ACE/CHI and NOCs.
Ability to effectively work as part of a team.
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
You will collaborate closely with design and verification engineers in projects, perform hands-on verification, and provide guidance to other verification engineers.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create a constrained-random verification environment using SystemVerilog.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
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